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CD4011BMS, CD4012BMS CD4023BMS
November 1994
CMOS NAND Gates
Pinouts
CD4011BMS TOP VIEW
Features
* High-Voltage Types (20V Rating) * Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V * Buffered Inputs and Outputs * Standardized Symmetrical Output Characteristics
A1 B2 J = AB 3
14 VDD 13 H 12 G 11 M = GH 10 L = EF 9E 8F
* Maximum Input Current of 1A at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC * 100% Tested for Maximum Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings
K = CD 4 C5 D6 VSS 7
* Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standards No. 13B, "Standard Specifications for Description of "B" Series CMOS Device's
J = ABCD 1 A2 B3
CD4012BMS TOP VIEW
14 VDD 13 K = EFGH 12 H 11 G 10 F 9E 8 NC NC = NO CONNECTION
Description
CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 Input CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4011BMS, CD4012BMS and the CD4023BMS is supplied in these 14 lead outline packages:
CD4011B CD4012B H4H H1B H3W CD4023B H4Q H1B H3W
C4 D5 NC 6 VSS 7
CD4023BMS TOP VIEW
A1 B2 D3 E4 F5 K = DEF 6 VSS 7
14 VDD 13 G 12 H 11 I 10 L = GHI 9 J = ABC 8C
Braze Seal DIP Frit Seal DIP Ceramic Flatpack
H4Q H1B H3W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3079
7-53
CD4011BMS, CD4012BMS, CD4023BMS Functional Diagrams
A B J K C D VSS
1 2 3 4 5 6 7
J = AB
14 13 12
VDD H G M L E F
K = CD L = EF
11 10 9 8
M = GH
CD4011BMS
J A B C D NC VSS
1 2 3 4 5 6 7
J = ABCD
14 13 12 11 10 9
VDD K H G F E NC NC = NO CONNECTION
K = EFGH
8
CD4012BMS
A B D E F K VSS
1 2 3 4 L = GHI 5 6 7 J = ABC
14 13 12 11 10 9 8
VDD G H I L J C
K = DEF
CD4023BMS
7-54
Specifications CD4011BMS, CD4012BMS, CD4023BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25
oC
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -
MAX 0.5 50 0.5 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+125oC -55oC +25o C
+125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC
+25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 0.53 1.4 3.5 -2.8 0.7
VOH > VOL < VDD/2 VDD/2
1.5 4 -
V V V V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-55
Specifications CD4011BMS, CD4012BMS, CD4023BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 250 338 200 270 UNITS ns ns ns ns
PARAMETER Propagation Delay
SYMBOL TPHL TPLH TTHL TTLH
CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND
Transition Time
+25oC +125oC, -55oC
NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125 C VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC
oC o o o
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 7 -
MAX 0.25 7.5 0.5 15 0.5 30 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 120 90
UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns
+125 Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
Input Voltage Low Input Voltage High Propagation Delay
VIL VIH TPHL TPLH
VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V
1, 2 1, 2 1, 2, 3 1, 2, 3
7-56
Specifications CD4011BMS, CD4012BMS, CD4023BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Transition Time SYMBOL TTHL TTLH CIN CONDITIONS VDD = 10V VDD = 15V Any Input NOTES 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25 C +25oC
o
MIN -
MAX 100 80 7.5
UNITS ns ns pF
Input Capacitance NOTES:
1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VNTH VPTH VPTH F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25 C +25oC +25oC +25oC +25oC +25oC
o
MIN -2.8 0.2 VOH > VDD/2 -
MAX 2.5 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit
UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - SSI Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.1A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
7-57
Specifications CD4011BMS, CD4012BMS, CD4023BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 25kHz
PART NUMBER CD4011B Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 3, 4, 10, 11 3, 4, 10, 11 3, 4, 10, 11 1, 2, 5 - 9, 12, 13 7 7 7 14 1, 2, 5, 6, 8, 9, 12 - 14 14 1, 2, 5, 6, 8, 9, 12 - 14 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12, 13
PART NUMBER CD4012B Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 1, 6, 8, 13 1, 6, 8, 13 6, 8 1, 6, 8, 13 2 - 5, 7, 9 - 12 7 7 7 14 2 - 5, 9 - 12, 14 14 2 - 5, 9 - 12, 14 1, 13 2 - 5, 9 - 12
PART NUMBER CD4023B Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V 6, 9, 10 6, 9, 10 6, 9, 10 1 - 5, 7, 8, 11 - 13 7 7 7 14 1 - 5, 8, 11 - 14 14 1 - 5, 8, 11 - 14 6, 9, 10 1 - 5, 8, 11 - 13
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7-58
CD4011BMS, CD4012BMS, CD4023BMS Schematic and Logic Diagrams
14 VDD VDD p 3*(1, 11) p 4*(2, 12) 3 (10, 4, 11) n VDD n n 5*(8, 13) p n n 6(9, 10) VDD 7 VSS n n n n p p n p 14
p 1* n (8, 6, 13) 2* (9, 5, 12) n p
p
p
p
p
VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK VSS 1 OF 4 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR OTHER GATES) VSS 7 1 OF 3 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR OTHER GATES)
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK 3(1, 11)
1(8, 6,13) 3 (10, 4, 11) 2(9, 5, 12) LOGIC DIAGRAM 4(2, 12) LOGIC DIAGRAM 6 (9, 10) 5(8, 13)
CD4011BMS
CD4023BMS
p 2*(12) n p
14
VDD
2(12)
p
3(11)
1 (13)
4(10) p
3*(11) n p 4*(10) n p 5*(9) n
5(9)
LOGIC DIAGRAM
VDD p
p
p 1
VSS
1 OF 2 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR OTHER GATES)
n n n n n
(13)
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK
7
VSS
CD4012BMS
7-59
CD4011BMS, CD4012BMS, CD4023BMS Typical Performance Characteristics
POWER DISSIPATION PER GATE (PD) (W) AMBIENT TEMPERATURE (TA) = +25oC 105
o 8 AMBIENT TEMPERATURE (TA) = +25 C 6 4
OUTPUT VOLTAGE (VO) (V)
SUPPLY VOLTAGE (VDD) = 15V 15
2
SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V
104 8
6 4 2
10V 10
103
8 6 4 2
5V 5
102
8 6 4 2
CL = 50pF CL = 15pF
2 4 68 2 4 68 2 4 68 2 4 68
10 0 5 10 15 INPUT VOLTAGE (VI) (V) 20 25 1 103 10 102 INPUT FREQUENCY (fI) (kHz) 104
FIGURE 1. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
FIGURE 2. TYPICAL POWER DISSIPATION CHARACTERISTICS
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
7-60
CD4011BMS, CD4012BMS, CD4023BMS Typical Performance Characteristics
200 PROPAGATION DELAY TIME PER GATE (tPHL, tPLH) (ns) 175 150 125 100 10V 75 50 25 0 10 15V SUPPLY VOLTAGE (VDD) = 5V AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
20
30
40
50
60
70
80
90
100
0 0
20
LOAD CAPACITANCE (CL) (pF)
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME PER GATE AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
Chip Dimensions and Pad Layouts
CD4011BMSH
CD4012BMSH
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)
CD4023BMSH
7-61

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